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From: (John R. Mashey)
Newsgroups: comp.arch
Subject: Re: Radiation and DRAM?
Date: 27 Nov 1995 18:50:59 GMT
Organization: Silicon Graphics, Inc.

In article <490n22$>, (David Miller) writes:

|> He also insisted that the cache sram was as susceptible to parity errors 
|> (I'll assume on a per-bit basis) and since it's not parity, having parity 
|> on the dram was silly.

In many current CPUs:

1) On-chip caches usually have byte parity. 
I don't know off-hand of anyone using ECC for the on-chip caches, since:
	a) The caches are fairly small.
	b) They usually need to support partial-word-writes, and would prefer
	to avoid the read-modify-write usually implied by ECC.
	c) This is especially clear if the on-chip cache is write-through
	anyway, i.e., there is likely to be a good copy of the data in the
	L2 cache.

2) Off-chip caches mostly use ECC.  (I think just about everybody does this
	with exception of UltraSparc.)
	a) The caches are much bigger.
	b) These caches are usually write-back, and hence may have the only
	copy of good data in the system.
	c) In a big SMP, there may be a fairly substantial amount of memory:
	for example, an SGI Challenge could have 36 R4400s, each with 4MB
	of cache, or 144MB total of cache.
-john mashey    DISCLAIMER: <generic disclaimer, I speak for me only, etc>
DDD:    415-933-3090	FAX: 415-967-8496
USPS:   Silicon Graphics 6L-005, 2011 N. Shoreline Blvd, Mountain View, CA 94039-7311

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