Newsgroups: comp.arch
From: mash@mash.wpd.sgi.com (John R. Mashey)
Subject: Re: Crays [really, why are word-sizes powers of 2?]
Date: Wed, 15 Sep 1993 02:56:06 GMT

Krste's explanation alluded some of the reasons, but one can perhaps be
at little more succinct, and in some cases, get to the more primordial
reasons.  This topic was discussed awhile back under the guise of
"why did you go from 32- to 64-bit, rather than just 48-bit].


In article <270n8n$r8n@agate.berkeley.edu>, krste@ICSI.Berkeley.EDU
(Krste Asanovic) writes:

|> In article <270j6n$o9n@news.u.washington.edu>,
|> tzs@hardy.u.washington.edu (Tim Smith) writes:
|>
|> |> For comp.arch readers, here's the question.  Duane Tokamine claims that
|> |> there are technical reasons for making the word size a power of two, but
|> |> has been unable to name them.  Can anyone name them, if they exist?
|> I think there's a considered, somewhat academic reason, and a very
|> simple practical reason.
....

My version: Main reason: S/360 design, i.e.:
        a) Byte addressing in machine required to also handle larger
           integers well [see below].
        b) 8-bit characters (bytes)

Had S/360s had 9-bit bytes, I suggest we'd mostly have 36-bit CPUs right now,
and starting to think about 72-bit CPUs.  Those who like floating point
would probably be happier, those who store a lot of characters not so happy.

Comment a) above essentially requires:
        a) Simple conversion from  address (of which there is one kind) to an
           index into a physical memory index, plus bits to select which bytes.
        b) Simple ability to iterate thru memory locations, regardless of size.
and *those* require that the partial words, words, whatever, be power-of-2
sized, not in number of bits, but number of smallest-addressable-units (bytes).

Consider machines
M32: 32-bit logical words and 32-bit physical words
M48: 48-bit logical words and physical words

Given the address X of a (byte, for example), consider how the hardware
needs to compute:
        XM: the index of the physical word in the memory array
        XO: the offset of the byte within the word, to control extraction
M32:    XM = X[31..2]                   pretty easy
        XO = X[1..0]
M48:    XM = (unsigned) X / 6           Oooh, bad! ... a divide in middle of
        XO = (unsigned) X % 6           likely critical path!

[Q: has *anyone* has ever built a machine that would do this? I know of none.]

Recall that once upon a time, many popular technical machines (IBM 709X,
UNIVAC 11xx, DEC PDP-10, GE600s) were 36-bit binary machines, and there
was at least one with 48-bit words (B5000, and CDC3600 (I think),
some 24s, and at least one 60-bitter (CDC 6600), and minis were 24,18,12, etc.
At least some of these:
1) Had instructions for accessing different-size bitfields across words.
2) Had  special byte-pointers and instructions to increment them to go
across words (which avoids the ugly divide/remainder above), i.e., you
can implement "Increment byte pointer and DePosit the Byte" reasonably.
3) Interesting combinations existed, like being able to support a few
partial-word sizes, or (like PDP-10) to use byte pointers that included:
        a word address
        a bit offset
        a size in bits
4) Character sizes were:
        6 (early on, and of course that didn't give you many characters)
                6 chars/word, OK, and word-addressed.
        7 (as on PDP-10, packed 5 to a word, with one extra bit)
        8 (could be done on PDP-10; OK on B5000)
        9 (I think several machines used this when needing >6)
        12 (I'd swear somebody did this)
        18 (actually, this was typical halfword, and a common word-address
           limit, to give you 256K of 36-bit words, a very large machine.)

5) Of course, some of the early commercial machines were character-oriented,
completely (i.e., IBM 1401, etc), but had little priority on fast binary
arithmetic.

Anyway, for various reasons, S/360 architects wanted 8-bit bytes, and then:
        16-bit words: too small for addressing
        24-bit words (3 bytes, not pow2)
        32-bit words OK
        48-bit words (6 bytes, not pow2)
        64-bit words (too expensive, especially for smaller S/360s .. remember
           that each register was precious stuff those days).

And after that,  IBM doing it meant there was increasing market pressure
for others to have 8-bit bytes as well ...  despite anguished cries from
some quarters (such as the PDP-10 folks dragged screaming onto the VAX :-)
and general muttering from floating-point users. By the mid-1970s,
any new, general-purpose machines had 8-bit bytes and 16- or 32-bit words,
and even Seymour switched from 60-bit to 64-bit.  The few major
exceptions are derivatives of architectures that started in 1960s, I think.
Anyway, the reason for 8/16/32 ... is thus a decision ~1960.

Anyway, had IBM chosen 9-bit bytes, I bet we'd have 36- and 72-bit IEEE..

-john mashey    DISCLAIMER: <generic disclaimer, I speak for me only, etc>
UUCP:    mash@sgi.com 
DDD:    415-390-3090	FAX: 415-967-8496
USPS:   Silicon Graphics 6L-005, 2011 N. Shoreline Blvd, Mountain View, CA 94039-7311