From: mash@mash.engr.sgi.com (John R. Mashey)
Newsgroups: comp.arch
Subject: Re: Why no more SRAM main memories?
Date: 4 Jan 1999 18:53:38 GMT

In article <915371392.793584@haldjas.folklore.ee>, Sander Vesik
<sander@haldjas.folklore.ee> writes:

|> Perhaps if there actually was support for having SRAM memories in computers,
|> there would be people who would test it out and use it, leading to more
|> more justifiable prices as the end result?

I don't think this is very likely.
The proposition has several implied beliefs:
	(a) There is no support for SRAM memories in computers [no].
	(b) People don't know what to do with SRAM [no]

High-end vector supercomputers have of course had SRAM main memories for
years, and lately, even the vector market is going more towards DRAM
(i.e., observe T90 versus J90), and of course, scalar microprocessors are
being used more and more often, although certain codes remain better
matched to vector systems.

There are certain codes (think of hashing keys into a hash table much
larger than any cache, retrieving 32 or 64-bits).  The only thing that
helps you is low-latency memory acess, and caches simply get in the way,
and the people who do this like vector machines with low-latency memory
systems.

Finally, there are, of course, plenty of systems with 4MB or 8MB SRAM cache
memories. Many algorithms are very amenable to explicit use of the caches,
and they do, in live practice.

Put another way, there are larege numbers of people in the world who have
experience in using SRAM memories, and most (but not all) have voted with
their $$ to use DRAM main memories.  I have had a few customers ask about
SRAM main memory for Origins, but most got uninterested when the
tradeoffs became clear.

With regard to DBMS applications, others have covered this, except nobody
mentioned the worst issue for many DBMS apps, which is disk latency.

Suppose we assume, picking simple numbers:

CPU: 500Mhz, 2ns, 4-issue
Main memory: 200ns (i.e., a big-memory system, and not just DRAM time)
Disk: 5millisec seek = 5000 microsecs = 5,000,000ns [good disk]

Hence simple latency ratios:
CPU cycle	1
memory		100
disk		2,500,000

Suppose you sustained 2 instructions/clock; this means that
a memory access = 	200 instructions
a disk access = 	5,000,000 instructions.

Some disk accesses cannot be gotten rid of, but others may be eliminated
via large physical memories to cache:
	1) small relational tables,
	2) index blocks (i.e., the intermediate pointers to the data).
Occasionally, it might be worthwhile fitting an entire database into memory,
but since disks are growing as fast or faster than DRAM these days,
this is often impractical, as many machiens already have TB disk farms.

But, in any case, for the same price, many people would buy bigger DRAM
memories (to eliminate some disk accesses), rather than smaller SRAM main
memories.




--
-john mashey    DISCLAIMER: <generic disclaimer: I speak for me only...>
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